(1) Field of the Invention
This invention relates generally to Magnetic Random Access Memories (MRAM) and relates more specifically to current driver design for write circuits of MRAM using Magnet Tunnel Junction (MTJ).
(2) Description of the Prior Art
In order to write the MTJ cells in a field MRAM, external magnetic field is applied in the x and y direction parallel to the tunnel junction. In practice, the magnetic field is generated by currents flowing in the word line and the bit line of the memory array. The lower boundary of the current is set to guarantee all MTJ cells can be written (full select requirement), while the upper boundary is set to guarantee that other cells in the same bit line are not written (half select requirement). Therefore, accurate current is required for the bit line or the word line current drivers.
FIG. 1a+b prior art show the conventional way to generate accurate current using current mirrors. It consists of three transistors. M1 is a reference transistor where its drain and gate are connected.
M2 is the output transistors with the same gate bias as M1. The reference current is generated from bandgap or other current references which are usually in DC or are slow due to accuracy and feedback. The current driver can be achieved by inserting a switch in the gate or the drain of the output transistor. A simple switch can be implemented using another transistor M3. When the switch is closed, the gate voltage is disturbed by the charge sharing of the gate capacitor in FIG. 1a prior art, or by voltage increase in the channel of the output transistor in FIG. 1b prior art. In both cases, the settling time of the output current is approximate Cg/gm, where Cg is the total gate capacitance of the two transistors M1 and M2 and gm is the trans-conductance of the reference transistor M1. We can see that Cg must be small and gm must be big to achieve high speed. However, Cg is usually big to reduce mismatch and to achieve larger multiplication factor of current amplification. The only way to achieve high speed and maintain accuracy is to increase gm, which implies increasing reference current. The reference current contributes to the standby current of MRAM chip. Typical standby current for our previous 4M-bit MRAM chip is on the order of 10 mA, mostly for the reference current of the write circuit.
It is a challenge for engineers to design a fast and accurate current driver.
There are known patents or patent publications dealing with write circuits for MRAMs.
U.S. Patent Publication (US 2007/0171703 to Huang et al.) proposes a current source for magnetic random access memory (MRAM), including a band-gap reference circuit, a first stage buffer, and a plurality of second stage buffers. The band-gap reference circuit provides an output reference voltage, which is locked by the first stage buffer. The plurality of second stage buffers generate a stable voltage in response to the locked voltage, so as to provide a current for the conducting wire after being converted, such that magnetic memory cell changes its memory state in response to the current. The current source may reduce the discharge time under the operation of biphase current, so as to raise the operating speed. Further, the circuit area of the current source for the MRAM is also reduced. The operation of multiple write wires may be provided simultaneously to achieve parallel write.
U.S. Patent Publication (US 2009/0237988 to Kurose et al.) discloses a magnetic memory device including a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting.
U.S. Patent Publication (US 2009/0161423 to Sugibayashi et al.) discloses an MRAM having a first cell array group and a second cell array group containing a plurality of cell arrays. Each of the first cell array group and the second cell array group includes a first current source unit for supplying a first write current IWBL to a bit line WBL of the cell array and a first current waveform shaping unit having a first capacitor requiring precharge and shaping the waveform of the first write current IWBL. When the cell array performs write into a magnetic memory, the first current waveform shaping unit of the first cell array group and the first current waveform shaping unit of the second cell array group charges and discharges electric charge accumulated in the first capacitor to wiring toward the bit line WBL at different periods from each other.
Furthermore the following publication is dealing with current reference circuits:    P. Allen and D. Holberg, “CMOS Analog Circuit design”, Oxford University Press.